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<div class="header">
  <div class="summary">
<a href="classunrolls_1_1trsm-members.html">List of all members</a> &#124;
<a href="#pub-static-methods">Static Public Member Functions</a>  </div>
  <div class="headertitle">
<div class="title">unrolls::trsm&lt; Scalar &gt; Class Template Reference</div>  </div>
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<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><h3>template&lt;typename Scalar&gt;<br />
class unrolls::trsm&lt; Scalar &gt;</h3>

<p>Unrolls for triSolveKernel</p>
<p>Idea: 1) Load a block of right-hand sides to registers in RHSInPacket (using loadRHS). 2) Do triangular solve with RHSInPacket and a small block of A (triangular matrix) stored in AInPacket (using triSolveMicroKernel). 3) Store final results (in avx registers) back into memory (using storeRHS).</p>
<p>RHSInPacket uses at most EIGEN_AVX_MAX_NUM_ACC avx registers and AInPacket uses at most EIGEN_AVX_MAX_NUM_ROW registers. </p>
</div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-static-methods"></a>
Static Public Member Functions</h2></td></tr>
<tr class="memitem:a70242ad9fc8a3c5c2be217db2599bfd5"><td class="memTemplParams" colspan="2">template&lt;int64_t currM, int64_t endK, int64_t counter&gt; </td></tr>
<tr class="memitem:a70242ad9fc8a3c5c2be217db2599bfd5"><td class="memTemplItemLeft" align="right" valign="top">static EIGEN_ALWAYS_INLINE std::enable_if_t&lt;(counter &gt; 0 &amp;&amp;currM &gt;=0)&gt;&#160;</td><td class="memTemplItemRight" valign="bottom"><a class="el" href="classunrolls_1_1trsm.html#a70242ad9fc8a3c5c2be217db2599bfd5">aux_divRHSByDiag</a> (PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;RHSInPacket, PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ROW &gt; &amp;AInPacket)</td></tr>
<tr class="separator:a70242ad9fc8a3c5c2be217db2599bfd5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af090fabfc33077a4f1ce496beb93ace0"><td class="memTemplParams" colspan="2">template&lt;bool isFWDSolve, int64_t endM, int64_t endK, int64_t counter, bool krem&gt; </td></tr>
<tr class="memitem:af090fabfc33077a4f1ce496beb93ace0"><td class="memTemplItemLeft" align="right" valign="top">static EIGEN_ALWAYS_INLINE std::enable_if_t&lt;(counter &gt; 0)&gt;&#160;</td><td class="memTemplItemRight" valign="bottom"><a class="el" href="classunrolls_1_1trsm.html#af090fabfc33077a4f1ce496beb93ace0">aux_loadRHS</a> (Scalar *B_arr, int64_t LDB, PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;RHSInPacket, int64_t rem=0)</td></tr>
<tr class="separator:af090fabfc33077a4f1ce496beb93ace0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1103a158e2b6492adc4dea5cdd272bec"><td class="memTemplParams" colspan="2">template&lt;bool isFWDSolve, int64_t endM, int64_t endK, int64_t counter, bool krem&gt; </td></tr>
<tr class="memitem:a1103a158e2b6492adc4dea5cdd272bec"><td class="memTemplItemLeft" align="right" valign="top">static EIGEN_ALWAYS_INLINE std::enable_if_t&lt;(counter &gt; 0)&gt;&#160;</td><td class="memTemplItemRight" valign="bottom"><a class="el" href="classunrolls_1_1trsm.html#a1103a158e2b6492adc4dea5cdd272bec">aux_storeRHS</a> (Scalar *B_arr, int64_t LDB, PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;RHSInPacket, int64_t rem=0)</td></tr>
<tr class="separator:a1103a158e2b6492adc4dea5cdd272bec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4d480998d431a42c023c875e2ed761bd"><td class="memTemplParams" colspan="2">template&lt;bool isARowMajor, bool isFWDSolve, bool isUnitDiag, int64_t endM, int64_t counter, int64_t numK&gt; </td></tr>
<tr class="memitem:a4d480998d431a42c023c875e2ed761bd"><td class="memTemplItemLeft" align="right" valign="top">static EIGEN_ALWAYS_INLINE std::enable_if_t&lt;(counter &gt; 0)&gt;&#160;</td><td class="memTemplItemRight" valign="bottom"><a class="el" href="classunrolls_1_1trsm.html#a4d480998d431a42c023c875e2ed761bd">aux_triSolveMicroKernel</a> (Scalar *A_arr, int64_t LDA, PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;RHSInPacket, PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ROW &gt; &amp;AInPacket)</td></tr>
<tr class="separator:a4d480998d431a42c023c875e2ed761bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a02a18d6cd18b19266553ec8e49610cb3"><td class="memTemplParams" colspan="2">template&lt;bool isARowMajor, bool isFWDSolve, bool isUnitDiag, int64_t initM, int64_t endM, int64_t endK, int64_t counter, int64_t currentM&gt; </td></tr>
<tr class="memitem:a02a18d6cd18b19266553ec8e49610cb3"><td class="memTemplItemLeft" align="right" valign="top">static EIGEN_ALWAYS_INLINE std::enable_if_t&lt;(counter &gt; 0)&gt;&#160;</td><td class="memTemplItemRight" valign="bottom"><a class="el" href="classunrolls_1_1trsm.html#a02a18d6cd18b19266553ec8e49610cb3">aux_updateRHS</a> (Scalar *A_arr, int64_t LDA, PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;RHSInPacket, PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ROW &gt; &amp;AInPacket)</td></tr>
<tr class="separator:a02a18d6cd18b19266553ec8e49610cb3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad7774daca78db31524c4ba2932ca58e4"><td class="memTemplParams" colspan="2">template&lt;int64_t currM, int64_t endK&gt; </td></tr>
<tr class="memitem:ad7774daca78db31524c4ba2932ca58e4"><td class="memTemplItemLeft" align="right" valign="top">static EIGEN_ALWAYS_INLINE void&#160;</td><td class="memTemplItemRight" valign="bottom"><a class="el" href="classunrolls_1_1trsm.html#ad7774daca78db31524c4ba2932ca58e4">divRHSByDiag</a> (PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;RHSInPacket, PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ROW &gt; &amp;AInPacket)</td></tr>
<tr class="separator:ad7774daca78db31524c4ba2932ca58e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aae8875f3996f74f9e2b5fec959ae798c"><td class="memTemplParams" colspan="2">template&lt;bool isFWDSolve, int64_t endM, int64_t endK, bool krem = false&gt; </td></tr>
<tr class="memitem:aae8875f3996f74f9e2b5fec959ae798c"><td class="memTemplItemLeft" align="right" valign="top">static EIGEN_ALWAYS_INLINE void&#160;</td><td class="memTemplItemRight" valign="bottom"><a class="el" href="classunrolls_1_1trsm.html#aae8875f3996f74f9e2b5fec959ae798c">loadRHS</a> (Scalar *B_arr, int64_t LDB, PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;RHSInPacket, int64_t rem=0)</td></tr>
<tr class="separator:aae8875f3996f74f9e2b5fec959ae798c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a94d6a0b7d713783fe16ebe538a864da4"><td class="memTemplParams" colspan="2">template&lt;bool isFWDSolve, int64_t endM, int64_t endK, bool krem = false&gt; </td></tr>
<tr class="memitem:a94d6a0b7d713783fe16ebe538a864da4"><td class="memTemplItemLeft" align="right" valign="top">static EIGEN_ALWAYS_INLINE void&#160;</td><td class="memTemplItemRight" valign="bottom"><a class="el" href="classunrolls_1_1trsm.html#a94d6a0b7d713783fe16ebe538a864da4">storeRHS</a> (Scalar *B_arr, int64_t LDB, PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;RHSInPacket, int64_t rem=0)</td></tr>
<tr class="separator:a94d6a0b7d713783fe16ebe538a864da4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5b0a976f64dcc6884fd22b54ecef6d92"><td class="memTemplParams" colspan="2">template&lt;bool isARowMajor, bool isFWDSolve, bool isUnitDiag, int64_t endM, int64_t numK&gt; </td></tr>
<tr class="memitem:a5b0a976f64dcc6884fd22b54ecef6d92"><td class="memTemplItemLeft" align="right" valign="top">static EIGEN_ALWAYS_INLINE void&#160;</td><td class="memTemplItemRight" valign="bottom"><a class="el" href="classunrolls_1_1trsm.html#a5b0a976f64dcc6884fd22b54ecef6d92">triSolveMicroKernel</a> (Scalar *A_arr, int64_t LDA, PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;RHSInPacket, PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ROW &gt; &amp;AInPacket)</td></tr>
<tr class="separator:a5b0a976f64dcc6884fd22b54ecef6d92"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2c11c1340f4c9804efe3572f3e408c40"><td class="memTemplParams" colspan="2">template&lt;bool isARowMajor, bool isFWDSolve, bool isUnitDiag, int64_t startM, int64_t endM, int64_t endK, int64_t currentM&gt; </td></tr>
<tr class="memitem:a2c11c1340f4c9804efe3572f3e408c40"><td class="memTemplItemLeft" align="right" valign="top">static EIGEN_ALWAYS_INLINE void&#160;</td><td class="memTemplItemRight" valign="bottom"><a class="el" href="classunrolls_1_1trsm.html#a2c11c1340f4c9804efe3572f3e408c40">updateRHS</a> (Scalar *A_arr, int64_t LDA, PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;RHSInPacket, PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ROW &gt; &amp;AInPacket)</td></tr>
<tr class="separator:a2c11c1340f4c9804efe3572f3e408c40"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Member Function Documentation</h2>
<a id="a70242ad9fc8a3c5c2be217db2599bfd5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a70242ad9fc8a3c5c2be217db2599bfd5">&#9670;&nbsp;</a></span>aux_divRHSByDiag()</h2>

<div class="memitem">
<div class="memproto">
<div class="memtemplate">
template&lt;typename Scalar &gt; </div>
<div class="memtemplate">
template&lt;int64_t currM, int64_t endK, int64_t counter&gt; </div>
<table class="mlabels">
  <tr>
  <td class="mlabels-left">
      <table class="memname">
        <tr>
          <td class="memname">static EIGEN_ALWAYS_INLINE std::enable_if_t&lt;(counter &gt; 0 &amp;&amp; currM &gt;= 0)&gt; <a class="el" href="classunrolls_1_1trsm.html">unrolls::trsm</a>&lt; Scalar &gt;::aux_divRHSByDiag </td>
          <td>(</td>
          <td class="paramtype">PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;&#160;</td>
          <td class="paramname"><em>RHSInPacket</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ROW &gt; &amp;&#160;</td>
          <td class="paramname"><em>AInPacket</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
  </td>
  <td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
  </tr>
</table>
</div><div class="memdoc">
<p>aux_divRHSByDiag</p>
<p>currM may be -1, (currM &gt;=0) in enable_if checks for this</p>
<p>1-D unroll for(startK = 0; startK &lt; endK; startK++) </p>

</div>
</div>
<a id="af090fabfc33077a4f1ce496beb93ace0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#af090fabfc33077a4f1ce496beb93ace0">&#9670;&nbsp;</a></span>aux_loadRHS()</h2>

<div class="memitem">
<div class="memproto">
<div class="memtemplate">
template&lt;typename Scalar &gt; </div>
<div class="memtemplate">
template&lt;bool isFWDSolve, int64_t endM, int64_t endK, int64_t counter, bool krem&gt; </div>
<table class="mlabels">
  <tr>
  <td class="mlabels-left">
      <table class="memname">
        <tr>
          <td class="memname">static EIGEN_ALWAYS_INLINE std::enable_if_t&lt;(counter &gt; 0)&gt; <a class="el" href="classunrolls_1_1trsm.html">unrolls::trsm</a>&lt; Scalar &gt;::aux_loadRHS </td>
          <td>(</td>
          <td class="paramtype">Scalar *&#160;</td>
          <td class="paramname"><em>B_arr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int64_t&#160;</td>
          <td class="paramname"><em>LDB</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;&#160;</td>
          <td class="paramname"><em>RHSInPacket</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int64_t&#160;</td>
          <td class="paramname"><em>rem</em> = <code>0</code>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
  </td>
  <td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
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</div><div class="memdoc">
<p>aux_loadRHS</p>
<p>2-D unroll for(startM = 0; startM &lt; endM; startM++) for(startK = 0; startK &lt; endK; startK++) </p>

</div>
</div>
<a id="a1103a158e2b6492adc4dea5cdd272bec"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a1103a158e2b6492adc4dea5cdd272bec">&#9670;&nbsp;</a></span>aux_storeRHS()</h2>

<div class="memitem">
<div class="memproto">
<div class="memtemplate">
template&lt;typename Scalar &gt; </div>
<div class="memtemplate">
template&lt;bool isFWDSolve, int64_t endM, int64_t endK, int64_t counter, bool krem&gt; </div>
<table class="mlabels">
  <tr>
  <td class="mlabels-left">
      <table class="memname">
        <tr>
          <td class="memname">static EIGEN_ALWAYS_INLINE std::enable_if_t&lt;(counter &gt; 0)&gt; <a class="el" href="classunrolls_1_1trsm.html">unrolls::trsm</a>&lt; Scalar &gt;::aux_storeRHS </td>
          <td>(</td>
          <td class="paramtype">Scalar *&#160;</td>
          <td class="paramname"><em>B_arr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int64_t&#160;</td>
          <td class="paramname"><em>LDB</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;&#160;</td>
          <td class="paramname"><em>RHSInPacket</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int64_t&#160;</td>
          <td class="paramname"><em>rem</em> = <code>0</code>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
  </td>
  <td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
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</div><div class="memdoc">
<p>aux_storeRHS</p>
<p>2-D unroll for(startM = 0; startM &lt; endM; startM++) for(startK = 0; startK &lt; endK; startK++) </p>

</div>
</div>
<a id="a4d480998d431a42c023c875e2ed761bd"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a4d480998d431a42c023c875e2ed761bd">&#9670;&nbsp;</a></span>aux_triSolveMicroKernel()</h2>

<div class="memitem">
<div class="memproto">
<div class="memtemplate">
template&lt;typename Scalar &gt; </div>
<div class="memtemplate">
template&lt;bool isARowMajor, bool isFWDSolve, bool isUnitDiag, int64_t endM, int64_t counter, int64_t numK&gt; </div>
<table class="mlabels">
  <tr>
  <td class="mlabels-left">
      <table class="memname">
        <tr>
          <td class="memname">static EIGEN_ALWAYS_INLINE std::enable_if_t&lt;(counter &gt; 0)&gt; <a class="el" href="classunrolls_1_1trsm.html">unrolls::trsm</a>&lt; Scalar &gt;::aux_triSolveMicroKernel </td>
          <td>(</td>
          <td class="paramtype">Scalar *&#160;</td>
          <td class="paramname"><em>A_arr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int64_t&#160;</td>
          <td class="paramname"><em>LDA</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;&#160;</td>
          <td class="paramname"><em>RHSInPacket</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ROW &gt; &amp;&#160;</td>
          <td class="paramname"><em>AInPacket</em>&#160;</td>
        </tr>
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          <td></td>
          <td>)</td>
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        </tr>
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<p>aux_triSolverMicroKernel</p>
<p>1-D unroll for(startM = 0; startM &lt; endM; startM++) </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a02a18d6cd18b19266553ec8e49610cb3">&#9670;&nbsp;</a></span>aux_updateRHS()</h2>

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template&lt;typename Scalar &gt; </div>
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template&lt;bool isARowMajor, bool isFWDSolve, bool isUnitDiag, int64_t initM, int64_t endM, int64_t endK, int64_t counter, int64_t currentM&gt; </div>
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          <td class="memname">static EIGEN_ALWAYS_INLINE std::enable_if_t&lt;(counter &gt; 0)&gt; <a class="el" href="classunrolls_1_1trsm.html">unrolls::trsm</a>&lt; Scalar &gt;::aux_updateRHS </td>
          <td>(</td>
          <td class="paramtype">Scalar *&#160;</td>
          <td class="paramname"><em>A_arr</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int64_t&#160;</td>
          <td class="paramname"><em>LDA</em>, </td>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;&#160;</td>
          <td class="paramname"><em>RHSInPacket</em>, </td>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ROW &gt; &amp;&#160;</td>
          <td class="paramname"><em>AInPacket</em>&#160;</td>
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          <td>)</td>
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<p>aux_updateRHS</p>
<p>2-D unroll for(startM = initM; startM &lt; endM; startM++) for(startK = 0; startK &lt; endK; startK++) </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ad7774daca78db31524c4ba2932ca58e4">&#9670;&nbsp;</a></span>divRHSByDiag()</h2>

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template&lt;typename Scalar &gt; </div>
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template&lt;int64_t currM, int64_t endK&gt; </div>
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          <td class="memname">static EIGEN_ALWAYS_INLINE void <a class="el" href="classunrolls_1_1trsm.html">unrolls::trsm</a>&lt; Scalar &gt;::divRHSByDiag </td>
          <td>(</td>
          <td class="paramtype">PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;&#160;</td>
          <td class="paramname"><em>RHSInPacket</em>, </td>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ROW &gt; &amp;&#160;</td>
          <td class="paramname"><em>AInPacket</em>&#160;</td>
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          <td>)</td>
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<p>Only used if Triangular matrix has non-unit diagonal values </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aae8875f3996f74f9e2b5fec959ae798c">&#9670;&nbsp;</a></span>loadRHS()</h2>

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template&lt;typename Scalar &gt; </div>
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template&lt;bool isFWDSolve, int64_t endM, int64_t endK, bool krem = false&gt; </div>
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          <td class="memname">static EIGEN_ALWAYS_INLINE void <a class="el" href="classunrolls_1_1trsm.html">unrolls::trsm</a>&lt; Scalar &gt;::loadRHS </td>
          <td>(</td>
          <td class="paramtype">Scalar *&#160;</td>
          <td class="paramname"><em>B_arr</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int64_t&#160;</td>
          <td class="paramname"><em>LDB</em>, </td>
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          <td class="paramkey"></td>
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          <td class="paramtype">PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;&#160;</td>
          <td class="paramname"><em>RHSInPacket</em>, </td>
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          <td class="paramname"><em>rem</em> = <code>0</code>&#160;</td>
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          <td>)</td>
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<p>Load endMxendK block of B to RHSInPacket Masked loads are used for cases where endK is not a multiple of PacketSize </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a94d6a0b7d713783fe16ebe538a864da4">&#9670;&nbsp;</a></span>storeRHS()</h2>

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template&lt;typename Scalar &gt; </div>
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template&lt;bool isFWDSolve, int64_t endM, int64_t endK, bool krem = false&gt; </div>
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          <td class="memname">static EIGEN_ALWAYS_INLINE void <a class="el" href="classunrolls_1_1trsm.html">unrolls::trsm</a>&lt; Scalar &gt;::storeRHS </td>
          <td>(</td>
          <td class="paramtype">Scalar *&#160;</td>
          <td class="paramname"><em>B_arr</em>, </td>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int64_t&#160;</td>
          <td class="paramname"><em>LDB</em>, </td>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;&#160;</td>
          <td class="paramname"><em>RHSInPacket</em>, </td>
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          <td class="paramname"><em>rem</em> = <code>0</code>&#160;</td>
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          <td>)</td>
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<p>Load endMxendK block of B to RHSInPacket Masked loads are used for cases where endK is not a multiple of PacketSize </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a5b0a976f64dcc6884fd22b54ecef6d92">&#9670;&nbsp;</a></span>triSolveMicroKernel()</h2>

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template&lt;typename Scalar &gt; </div>
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template&lt;bool isARowMajor, bool isFWDSolve, bool isUnitDiag, int64_t endM, int64_t numK&gt; </div>
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          <td class="memname">static EIGEN_ALWAYS_INLINE void <a class="el" href="classunrolls_1_1trsm.html">unrolls::trsm</a>&lt; Scalar &gt;::triSolveMicroKernel </td>
          <td>(</td>
          <td class="paramtype">Scalar *&#160;</td>
          <td class="paramname"><em>A_arr</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int64_t&#160;</td>
          <td class="paramname"><em>LDA</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;&#160;</td>
          <td class="paramname"><em>RHSInPacket</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ROW &gt; &amp;&#160;</td>
          <td class="paramname"><em>AInPacket</em>&#160;</td>
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          <td>)</td>
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<p>endM: dimension of A. 1 &lt;= endM &lt;= EIGEN_AVX_MAX_NUM_ROW numK: number of avx registers to use for each row of B (ex fp32: 48 rhs =&gt; 3 avx reg used). 1 &lt;= endK &lt;= 3. isFWDSolve: true =&gt; forward substitution, false =&gt; backwards substitution isUnitDiag: true =&gt; triangular matrix has unit diagonal. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a2c11c1340f4c9804efe3572f3e408c40">&#9670;&nbsp;</a></span>updateRHS()</h2>

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template&lt;typename Scalar &gt; </div>
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template&lt;bool isARowMajor, bool isFWDSolve, bool isUnitDiag, int64_t startM, int64_t endM, int64_t endK, int64_t currentM&gt; </div>
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          <td class="memname">static EIGEN_ALWAYS_INLINE void <a class="el" href="classunrolls_1_1trsm.html">unrolls::trsm</a>&lt; Scalar &gt;::updateRHS </td>
          <td>(</td>
          <td class="paramtype">Scalar *&#160;</td>
          <td class="paramname"><em>A_arr</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int64_t&#160;</td>
          <td class="paramname"><em>LDA</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ACC &gt; &amp;&#160;</td>
          <td class="paramname"><em>RHSInPacket</em>, </td>
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          <td class="paramkey"></td>
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          <td class="paramtype">PacketBlock&lt; vec, EIGEN_AVX_MAX_NUM_ROW &gt; &amp;&#160;</td>
          <td class="paramname"><em>AInPacket</em>&#160;</td>
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          <td>)</td>
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<p>Update right-hand sides (stored in avx registers) Traversing along the column A_{i,currentM}, where currentM &lt;= i &lt;= endM, and broadcasting each value to AInPacket. </p>

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